The SCSI interface may be best described as a device independent input/output bus which allows a variety of peripheral devices to be connected to a personal computer system. SCSI refers to Small Computer Systems Interface, and was initially developed to provide a disk drive interface that supported logical addressing of data rather than the more prevalent physical addressing. In addition, the SCSI interface was developed to transfer information in parallel, byte-wise fashion instead of serially, thus, ending certain compatibility difficulties associated with developing new disk drive technologies and bringing them to the market place. The electrical characteristics and signal protocols of the SCSI interface were developed in such a manner that the requirements of various peripheral devices could be accommodated with relative ease and flexibility. In particular, the SCSI interface protocol defines a number of commands which are available for accessing and querying a particular peripheral device regarding the parameter set required for the device to operate correctly. This particular feature of the SCSI interface makes it possible for a system designer to write a software device driver program for a generalized peripheral device, without regard to specific parameter set details.
In accordance with various versions of the SCSI interface, such as SCSI-1, SCSI-2, and SCSI-3, anywhere from 8 to 32 individual peripheral devices can be addressed on an SCSI bus depending on whether the bus is an 8-bit bus, a 16-bit bus or a 32-bit bus. These devices are generally categorized as initiators and targets, with any particular peripheral device able to play either role at a particular point in time. Specifically, a peripheral device functioning as an initiator, is a device that initiates an information transaction or data transfer by giving another peripheral device a particular task to perform. An example of an initiator might well be the SCSI host adapter of a personal computer system, while an example of a typical target device might well be a rotating disk data storage system such as a hard disk drive or CD-ROM. A target peripheral device may be thus seen as a device which carries out the task identified by the initiator.
As mentioned previously, the SCSI bus may be from 8 to 32 bits wide, depending on configuration, with the conventional, SCSI-1 bus being an 8-bit wide bus comprising 18 separate signals; 8 data bits, a parity bit and 9 protocol signal lines, in addition to a five volt power supply line for termination. In accordance with the SCSI specification, these signals (with the exception of the terminator power supply) are either a single ended active-low signals or differential signals defined by output driver circuitry on the initiator and target devices. In accordance with the SCSI interface specification, the signal swing of output drivers from a, for example, SCSI controller chip is defined as a minimum V.sub.OL of about 0.8 volts to a maximum V.sub.OH of 3.7 volts DC. Although a larger V.sub.OH value would not necessarily degrade the signal performance of various SCSI integrated circuits coupled to the bus, taking V.sub.OH higher than about 3.8 volts does have a significant effect on the overall power consumption of an SCSI system.
In particular, because inactive signal lines of the bus are pulled-up to approximately 2.5 volts by terminators, it will be understood that if an active high from an output driver were to pull an inactive signal up to a value exceeding 3.5 volts to about 3.8 volts, a significant voltage differential would be established between an output driver in the pull-up state and the bus, thus causing significant amounts of current to be sourced to the bus resulting in disadvantageous drops along the bus and very high power consumption levels. In addition, this tendency would be substantially magnified were the SCSI bus to be heavily populated, and in a generally inactive state. Such a situation would likely obtain where an SCSI bus was coupled between the multiple initiators and multiple target devices and where a host computer was engaged in processing operations requiring very few peripheral calls.
Such constraints, on both signal swings and minimum and maximum output voltage levels, pose a significant challenge to an integrated circuit designer when attempting to develop circuits that communicate with the SCSI bus. Given the relatively small signal swings and the lack of significant head room between V.sub.OL and V.sub.OH, along with the need to maintain both of these quantities within relatively strictly defined limits, it will be further understood that SCSI circuit input receivers need to be able to accurately differentiate between high and low voltage levels, as well as translate these narrowly defined signals into rail-to-rail values suitable for further processing using CMOS integrated circuit technology.
Pertinent to these requirements is that SCSI input receivers need to be designed with a certain degree of hysteresis, such that there are well defined low and high level input threshold voltages. In particular, it is desirable for an SCSI input receiver to have an "input threshold high" (V.sub.IH) of about 1.75 volts and an "input threshold low" (V.sub.IL) of about 1.15 volts at nominal integrated circuit manufacturing process centers.
The prior art has developed various forms of integrated circuit input receivers with these particular signal response characteristics. One of the more common forms of threshold circuits comprising SCSI input receivers is a Schmitt trigger. FIG. 1 illustrates the voltage transfer characteristic of an ideal non-inverting Schmitt trigger circuit which is designed to be resistant to small variations of the input voltage and requires that the input voltage pass through high and low level trigger values in order to induce a change in the output. As shown generally in FIG. 1, the Schmitt trigger output characteristic follows voltage trace 1, such that the output signal V.sub.OUT does not rise until the input voltage V.sub.IN rises above a turn-on voltage threshold V.sub.IH. Likewise, the Schmitt trigger input voltage V.sub.IN must fall below a turn-off voltage threshold V.sub.IL, before the output voltage falls from its maximum value to about 0.0 volts, as indicated in voltage trace 2.
A prior art-type non-inverting CMOS Schmitt trigger circuit is depicted in the schematic circuit diagram of FIG. 2, and includes two source-drain series-connected p-channel transistors, 3 and 4, connected in series fashion with two source-drain series-connected n-channel transistors, 5 and 6. Each of the p-channel and n-channel series connected transistors have their gate terminals connected in common and to a signal input. An output is defined at the source-drain node between the p-channel series (transistors 3 and 4) and the n-channel series (transistors 5 and 6).
A third p-channel device 7 is coupled between ground potential and the source-drain junction node between the p-channel series transistors 3 and 4. Likewise, a third n-channel transistor 8 is coupled between the power supply voltage and the source-drain node between the n-channel series transistors 5 and 6. The gate terminals of the third transistors 7 and 8 are connected in common and to the output of the series stack.
In operation, it will be understood by those having skill in the art that the turn-on threshold voltage level V.sub.IH depends on the relative sizings of the n-channel transistors 5, 6 and 8, while the turn-off threshold voltage level V.sub.IL depends on the relative sizings of the p-channel transistors 3, 4 and 7. For example, in order to switch the output from high to low, the p-channel series stack (transistors 3 and 4) must overcome the grounding effects of p-channel transistor 7, while to switch the outputs from low to high, the n-channel stack (transistors 5 and 6) must overcome the effects of the supply voltage provided by n-channel transistor 8. The actual switch points of each of the circuit legs depends, necessarily, on providing the proper relative sizes for each of the transistors, in order to provide the appropriate degree of hysteresis.
While generally recognized as offering a reasonably cost-effective input receiver design with the necessary degree of hysteresis, conventional Schmitt triggers exhibit signal response characteristics which are found to be sensitive to variations in circuit temperature as well as variations in integrated circuit manufacturing process tolerances. Such variations in signal response significantly impact the voltage hysteresis and the circuit's speed, as well as its absolute switching points. Process tolerance variations often tend to either magnify or reduce the designed separation between the V.sub.IL and V.sub.IH thresholds, as those threshold voltages are caused to drift by process tolerance spread. This threshold voltage drift is particularly disadvantageous in SCSI systems, where the signal environment is predicated on terminated transmission lines with their attendant resonances and reflections.
Alternative prior art-type circuitry, which attempts to more particularly define input threshold voltages, typically include separate high and low level input sections, each comprising an input inverter configured with its own particular switching threshold voltage. As depicted in FIG. 2b, a particular inverter's switching threshold (V.sub.TH) is defined as the voltage developed when the input is shorted to the output. Each of the high and low level input sections would then be comprised of an inverter with its component transistors particularly sized to develop the necessary threshold voltage. In a manner similar to one which will be described in connection with FIG. 3, the outputs of the high and low level blocks would be multiplexed by logic gates to develop a unitary output. While these circuits are relatively simple in concept, it is generally understood that they are also quite sensitive to variations in circuit temperature as well as variations in integrated circuit manufacturing process tolerances. Accordingly, such circuits also exhibit performance deficiencies that make them disadvantageous for use in an SCSI input receiver.
Accordingly, it will be seen that there is a need for an input buffer for an SCSI input receiver with a definable hysteresis characteristic such that it switches about well defined high and low level input thresholds, and adequately translates SCSI bus signal characteristics to CMOS rail-to-rail levels. Such an input buffer should be able to internally develop both low and high level switching thresholds and, additionally, maintain the low and high level switching threshold voltage values across specification allowable temperature extremes and across integrated circuit manufacturing process tolerance corners.